The present invention relates to integrated circuit chips, and more specifically, to a design structure for upside-down field effect transistors.
Integrated circuits (ICs) are implemented using a plurality of interconnected field effect transistors (FETs), which can be realized as metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). The MOS transistor can include both a p-type device and an n-type device, wherein such a device is commonly referred to as a complimentary MOS or CMOS device. A MOS transistor includes a gate electrode as a control electrode that is formed over a semiconductor layer having spaced-apart source and drain regions formed therein. Because of the higher density per unit area of microelectronic devices on a chip, it is a challenge to reduce the parasitic or unwanted capacitance between the gate conductor line and the metal filled vias that form the contacts to the device source and drain.